ESD protection devices are utilized on integrated circuits (ICs) to prevent damage caused by ESD events, which often involve high voltage (e.g., several kV) and high current stress (e.g., 1-10 A) transferred to a host IC by way of contact with a charged object. Although ESD events typically have very short durations (e.g., 0.2-200 ns), the ESD current/voltage pulses can produce irreparable damage to ICs.
FIG. 7 depicts a simplified IC 10 including a conventional basic ESD protection device 11 that functions to protect IC 10 against ESD events. ESD protection circuit 11 is connected between a conductive signal path (wire) 12 and ground, where signal path 12 functions to pass signals between an input/output (I/O) pad 13 and an I/O circuit 14, which is turn is operably coupled to functional circuitry (not shown) of IC 10. IC 10 is typical designed and manufactured using an established semiconductor fabrication flow (e.g., CMOS) such that, while input signals VIN applied to I/O pad 13 are within the predetermined voltage and current ranges, ESD protection device 11 remains inactive (i.e., in a high impedance operating state), whereby input signals VIN are passed from conductive path 12 to I/O circuit 14, which in turn converts input signals VIN into data values that are then processed by the IC's functional circuitry. An ESD event occurs when a voltage potential is applied to I/O pad 13 that is outside (e.g., greater than) the predetermined voltage and/or current ranges. When such an ESD event occurs (i.e., when input voltage VIN on signal path 12 exceeds a predetermined “safe” voltage level), ESD protection device 11 activates by way of switching from its high-impedance state to a low-impedance state, thereby shunting the ESD voltage/current to ground, thus preventing damage to I/O circuit 14.
ESD protection device 11 (FIG. 7) is implemented using a conventional grounded-gate NMOS (ggNMOS) transistor 15, which represents a basic ESD protection device used in ICs. Conventional ggNMOS transistor 15 is similar to a normal NMOS transistor, but differs in that its gate G, its n-doped source S, and its p-doped body B are collectively connected to ground, with its n-doped drain ID connected to I/O pad 13 by way of signal path 12. In this configuration, ggNMOS transistor 15 functions as a parasitic NPN bipolar junction transistor (BJT) with n-doped drain D forming the BJT's collector, n-doped source S forming the BJT's emitter, and p-doped body B forming the BJT's base. A positive ESD event is generated on I/O pad 13 when input voltage VIN on signal path 12 exceeds the drain-to-source breakdown voltage BVDSS, of ggNMOS transistor 15, producing a positive current flow from drain D to source S (i.e., electrons flow to source S and holes flow to body B), which in turn generates a positive body-to-source voltage (VBS). Stated differently, using the above-mentioned parasitic NPN BJT analogy, the ESD event causes the collector-base junction to become reverse biased to the point of avalanche breakdown, whereby the positive current flowing from the base to ground induces a voltage potential across a parasitic resistor present between the emitter and base, which is produced by the finite conductivity of the p-doped body (substrate), causing a positive voltage to appear across the base-emitter junction. The positive base-emitter voltage forward biases this junction, triggering the parasitic NPN BJT, thereby shunting the ESD event to ground.
While conventional ggNMOS-type ESD protection device 11 was considered adequate for lower bandwidth IC circuits, for at least the following reasons they are inadequate for ICs configured to receive high-frequency, large amplitude input signals, such as the radio-frequency (RF) circuits utilized in modern communication devices (e.g., cellular telephones).
First, ggNMOS-type ESD protection device 11 provides unsymmetrical protection against positive ESD events. That is, as set forth above, ESD protection device 11 functions like a parasitic BJT when subjected to positive voltages, whereby it activates when subjected to positive voltages above the drain-to-source breakdown voltage (BVDSS) of ggNMOS transistor 15, which is typically 5V for a single NMOS device. In contrast, when subjected to negative voltages, ggNMOS transistor 15 functions like a diode (i.e., the gate, source and body terminals form the diode's anode, and the drain terminal forming the diode's cathode), whereby ESD protection device 11 activates when subjected to negative voltages above the diode's threshold voltage, which is typically 0.7V. This unsymmetrical activation at positive and negative ESD events makes ESD protection device 11 unsuitable for RF circuits that require symmetric ESD protection.
Second, in order to achieve a high trigger voltage (e.g., 70V), ESD protection device 11 must be configured using multiple ggNMOS transistors in a stacked arrangement, thereby causing the resulting stacked ggNMOS device to generate a large nonlinear capacitive loading on signal line 12. This large nonlinear capacitive loading has a greater impact on the performance of RF ICs than on lower bandwidth IC circuits. Specifically, at high frequencies and large amplitudes, this nonlinearity degrades the signal integrity of the high performance mixed signal circuits, such as analog-to-digital converters (ADCs), which are utilized in the I/O circuitry of RF circuits.
Several ESD protection devices have been developed for RF circuits that address the nonlinear capacitance issues associated with ggNMOS-based ESD protection devices. One conventional approach taught in U.S. Pat. No. 9,627,883 (Muthukrishnan et al.) utilizes two large FET devices connected in series between a signal line and ground, with the gate and source terminals of the two FETs being coupled together by way of a resistor network. With this arrangement, in response to a positive ESD event one of the two large FETs turns on in response to a high or low trigger voltage, and the other large FET acts as a parasitic diode to shunt the ESD charge to ground. The roles of the two large FETs reverse in response to a negative ESD event, thereby providing bi-directional ESD protection. A problem with such prior art RF ESD protection devices is that the two large FETs and associated resistors occupy a large chip area, making them relatively expensive to manufacture, and generate significant capacitive loading that produces harmonic interference, especially at a second harmonic level, which impedes optimal operation of the host RF circuit. Moreover, many such prior art RF ESD protection devices provide relatively low immunity to false triggering.
What is needed is a ESD protection device for RF circuits that addresses the problems associated with the conventional ESD protection devices mentioned above. In particular, what is needed is an ESD protection device that exhibits symmetrical bi-directional protection from both positive and negative ESD events, exhibits high immunity to false triggering, introduces minimal parasitic capacitive loading on the host RF circuit (i.e., exhibits low harmonics), and is inexpensive to produce (i.e., occupies a relatively small chip area and easily produced using established RF circuit fabrication process flows).